The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2004

Filed:

Oct. 17, 2000
Applicant:
Inventors:

Matthew Weldon, Phoenix, AZ (US);

Thomas Laursen, Tempe, AZ (US);

Malcolm Grief, Chandler, AZ (US);

Paul Holzapfel, Mercer, PA (US);

Mark A. Meloni, Lewisville, TX (US);

Robert Eaton, Scottsdale, AZ (US);

Assignee:

SpeedFam-IPEC Corporation, Chandler, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 4/912 ;
U.S. Cl.
CPC ...
B24B 4/912 ;
Abstract

The invention is a method and apparatus for planarizing a wafer. Discrete measurements are taken across the surface of the wafer at a desired spatial density. The measurements may be generated using a flash lamp to reflect a light signal off the surface of the wafer with a spectrometer analyzing the reflected light. A plurality of probes may be used at different locations to shorten the time necessary for taking measurements across the full front surface of the wafer and for allowing a plurality of areas to be sampled substantially simultaneously. A control system receives the measurements and their corresponding locations. The control system is then able to analyze the data looking for areas or bands on the front surface of the wafer that need an increase or decrease in material removal rate. The control system is then able to adjust one or more planarization parameters to improve the process for the current wafer or for future wafers.


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