The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2004

Filed:

Apr. 25, 2003
Applicant:
Inventors:

Young Kuk Park, Seoul, KR;

Byung Joon Han, Singapore, SG;

Jae Dong Kim, Tempe, AZ (US);

Assignee:

Amkor Technology, Inc., Chandler, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/150 ;
U.S. Cl.
CPC ...
H01L 2/150 ;
Abstract

A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patterns are provided proximate to the chip mounting region. Stacked semiconductor are disposed in the chip mounting region. Conductive wires are bonded between respective pads of one stacked chip and respective transfer patterns, and other conductive wires are bonded between respective pads of the other stacked chip and the same respective transfer patterns, thereby electrically connecting respective pads of the two chips through a pair of bond wires and an intermediate transfer pattern. The transfer patterns are separate from circuit patterns of the substrate. At least one of the first and second chips is electrically connected to some of the circuit patterns for external connection.


Find Patent Forward Citations

Loading…