The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2004
Filed:
Aug. 31, 2001
Toshiharu Furukawa, Essex Junction, VT (US);
Mark C. Hakey, Fairfax, VT (US);
Steven J. Holmes, Milton, VT (US);
David V. Horak, Essex Junction, VT (US);
James M. Leas, South Burlington, VT (US);
William H-L Ma, Fishkill, NY (US);
Paul A. Rabidoux, Winooski, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.