The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
May. 17, 2002
Kirk J. Strozewski, Round Rock, TX (US);
Kevin D. Lucas, Austin, TX (US);
Marc J. Olivares, New Braunfels, TX (US);
Chi-Min Yuan, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method ( ) for correcting lithography error includes generating ( ) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize ( ) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern ( ) has isolated features ( ) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern ( ) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.