The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2004
Filed:
Jul. 12, 2000
Geoffery Summers, Highland, MD (US);
Michael Xapsos, Alexandria, VA (US);
Eric Jackson, Bowie, MD (US);
The United States of America as represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.