The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2004

Filed:

Jun. 13, 2001
Applicant:
Inventors:

Stephen P. DeOrnellas, Santa Rosa, CA (US);

Alferd Cofer, Petaluma, CA (US);

Leslie G. Jerde, Novato, CA (US);

Kurt A. Olson, Sebastopol, CA (US);

Paritosh Rajora, Petaluma, CA (US);

Assignee:

Tegal Corporation, Petaluma, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01I 2/1302 ;
U.S. Cl.
CPC ...
H01I 2/1302 ;
Abstract

A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor and controlling the temperature of the wafer by controlling the pressure of the gas contacting the backside of the wafer and/or providing a heat source such as for example in the chuck or electrode associated with the wafer in order to heat the wafer


Find Patent Forward Citations

DeOrnellas, Stephen. (2004). Method for minimizing the critical dimension growth of a feature on a semiconductor wafer (U.S. Patent No. 6774046). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6774046

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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