The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6766507 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 20, 2004

Filed:

Apr. 12, 2002
Applicant:
Inventors:

James A. Bruce, Williston, VT (US);

Stephen E. Knight, Essex Junction, VT (US);

Joshua J. Krueger, Burlington, VT (US);

Matthew C. Nicholls, South Burlington, VT (US);

Jed H. Rankin, South Burlington, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.


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