The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6757110 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 29, 2004

Filed:

May. 29, 2002
Applicant:
Inventors:

Harry Sewell, Wilton, CT (US);

Jorge Ivaldi, Wilton, CT (US);

John Shamaly, Wilton, CT (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 9/00 ;
U.S. Cl.
CPC ...
G02B 9/00 ;
Abstract

The present invention relates to a lithography apparatus using catadioptric exposure optics that projects high quality images without image flip. The lithography apparatus includes a reticle stage, a wafer stage, and a catadioptric exposure optics located between the reticle stage and the wafer stage. The catadioptric exposure optics projects an image from the reticle stage onto the wafer stage. The projected image has the same image orientation as the image from the reticle stage. In other words, the catadioptric exposure optics does not perform image flip. The reticle stage lies on a first plane and the wafer stage lies on a second plane, where the first plane is orthogonal to the second plane. In another embodiment of the present invention, the catadioptric exposure optics projects an even number of reflections. The projected image is of high precision and lacks aberrations such as perspective warping and obscured areas. The invention can be combined with a dual wafer stage and with a dual isolation system.


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Sewell, Harry. (2004). Catadioptric lithography system and method with reticle stage orthogonal to wafer stage (U.S. Patent No. 6757110). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6757110

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