The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2004

Filed:

Jan. 30, 2003
Applicant:
Inventors:

Chii-Ping Chen, Hsinchu, TW;

Wen-Chen Chien, Hsin-Chu, TW;

Ching-Ming Tsai, Miaoli, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ;
Abstract

A method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process including providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.


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