The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6680221 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 20, 2004

Filed:

Oct. 10, 2002
Applicant:
Inventors:

Tetsuya Tokunaga, Takatsuki, JP;

Takahiro Yonezawa, Neyagawa, JP;

Hiroyuki Kiyomura, Takatsuki, JP;

Tatsuo Sasaoka, Osaka, JP;

Satoshi Horie, Kadoma, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A bare chip mounting method includes: a dicing step for dividing a semiconductor wafer into individual IC chips while the semiconductor wafer is being attached to a carrier; a washing step for washing the diced semiconductor wafer; a bump-bonding for carrying the washed semiconductor wafer to an assembly process while the semiconductor wafer is being attached to the carrier so as to form a bump on an electrode pad of the wafer; and a mounting step for mounting each of the IC chips, on which the bump is formed, onto a circuit formation body.


Find Patent Forward Citations

Tokunaga, Tetsuya. (2004). Bare chip mounting method and bare chip mounting system (U.S. Patent No. 6680221). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6680221

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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