The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2004

Filed:

Feb. 26, 2002
Applicant:
Inventors:

Toshiya Yokogawa, Nara, JP;

Kunimasa Takahashi, Osaka, JP;

Makoto Kitabatake, Nara, JP;

Osamu Kusumoto, Nara, JP;

Takeshi Uenoyama, Kyoto, JP;

Koji Miyazaki, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/9423 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; H01L 2/7095 ; H01L 2/900 ; H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/9423 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; H01L 2/7095 ; H01L 2/900 ; H01L 2/100 ;
Abstract

In a SiC substrate ( ), a first active region ( ) composed of n-type heavily doped layers ( ) and undoped layers ( ), which are alternately stacked, and a second active region ( ) composed of p-type heavily doped layers ( ) and undoped layers ( ), which are alternately stacked, are provided upwardly in this order. A Schottky diode ( ) and a pMOSFET ( ) are provided on the first active region ( ). An nMOSFET ( ), a capacitor ( ), and an inductor ( ) are provided on the second active region ( ). The Schottky diode ( ) and the MOSFETs ( ) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.


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