Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo sram cell

Abstract

A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.