The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2003
Filed:
Mar. 23, 2001
Applicant:
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract
A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer ( ) is formed over the dielectric layer ( ). A sacrificial layer ( ) is formed over the SiC layer ( ). A trench ( ) is etched in the sacrificial layer ( ), the SiC layer ( ) and the dielectric layer ( ). A sputter etch of the sacrificial layer ( ) is used to create a wider opening at a top of the sacrificial layer ( ) than at a top of the dielectric layer ( ). A barrier layer ( ) and copper seed layer ( ) are formed. The trench ( ) is then filled with copper ( ). CMP is used to remove the excess copper ( ) and barrier layer ( ) stopping on the SiC ( ).