The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
Dec. 03, 2001
Chen-Chin Liu, Yun Lin-Hsien, TW;
Chin-Yi Huang, Hsin-Chu Hsien, TW;
Weng-Hsing Huang, Hsin-Chu, TW;
Macronix International Co. Ltd., Hsin-Chu, TW;
Abstract
A semiconductor wafer includes a substrate, a polysilicon layer, and a sacrificial layer on the polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. A passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the sacrificial layer. The passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer, followed by removing the passivation layer and removing the sacrificial layer. A recess is thus formed with the polysilicon layer as the bottom of the recess and the remaining dielectric layer as the walls. Finally, another polysilicon layer is formed on the semiconductor wafer to form a floating gate.