The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Mar. 31, 2000
Farzin Karimi, Roslindale, MA (US);
Thompson W. Crosby, San Jose, CA (US);
V. Swamy Irrinki, Milpitas, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.