The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
May. 26, 2000
William J. Taylor, Jr., Round Rock, TX (US);
Marius Orlowski, Austin, TX (US);
David C. Gilmer, Austin, TX (US);
Prasad V. Alluri, Round Rock, TX (US);
Christopher C. Hobbs, Austin, TX (US);
Michael J. Rendon, Austin, TX (US);
Iuval R. Clejan, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Techniques for forming gate dielectric layers ( ) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions ( ) are formed prior to formation of structures included in the gate structure ( ) of the semiconductor device, where the gate structures ( ) are preferably formed using low temperature operations that allow the amorphous silicon regions ( ) to remain in an amorphous state. Source/drain regions ( ) are formed in the amorphous silicon regions ( ), and then the substrate is annealed to recrystallize the amorphous regions.