The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Apr. 23, 2002
Applicant:
Inventors:

Chung-Che Tsai, Taipei, TW;

Wei-Heng Shan, Hsinchu, TW;

Assignee:

UltraTera Corporation, Taiwan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second chip mounted on the first chip, is formed with a peripherally-situated cushion member, whereby bonding wires are adapted to extend from bond pads of the second chip in a direction parallel to the chip, and reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the second chip. By the above structure, the bonding wires would be firmly held in position to be free of contact or short circuit with the second chip, and overall package profile can be significantly miniaturized.


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