The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2003
Filed:
Sep. 26, 2000
Applicant:
Inventors:
Alec Morton, Plano, TX (US);
Taylor Efland, Richardson, TX (US);
Chin-yu Tsai, Plano, TX (US);
Jozef C. Mitros, Richardson, TX (US);
Dan M. Mosher, Plano, TX (US);
Sam Shichijo, Plano, TX (US);
Keith Kunz, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
Abstract
An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate ( ) is formed over a CMOS n-well region ( ) and a CMOS p-well region ( ) in a silicon substrate ( ). Transistor source regions ( ), ( ) and drain regions ( ), ( ) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions ( ), ( ) serve as the drain extension regions of the transistor.