Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer

Abstract

Two source/drain regions ( ) belonging to separate elements which are adjacent to each other are connected through a metal layer ( ) having the same height as a height of a metal layer ( ) forming a part of a gate electrode. In a manufacturing process, an insulating layer ( ) is made of other material than and inserted between two insulating layers ( ) and ( ). The two insulating layers ( ) and ( )function as molds for burying the metal layers ( ), ( ) and ( ) therein and made of the same material. The metal layer ( ) can therefore be formed at the same height as the height of the metal layer ( ). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.