The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2003
Filed:
Aug. 27, 2001
Kumar Nagarajan, San Jose, CA (US);
Seng Sooi Lim, San Jose, CA (US);
Chok J. Chia, Cupertino, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound. Fluid communication between the plurality of vias and the air space may be provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during processing of the substrate.