The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2003
Filed:
Feb. 15, 2002
Peter W. Lee, Saratoga, CA (US);
Hsing-Ya Tsao, San Jose, CA (US);
Tam Tran, San Jose, CA (US);
Fu-Chang Hsu, San Jose, CA (US);
Aplus Flash Technology Inc., San Jose, CA (US);
Abstract
A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.