The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Feb. 16, 2000
Kan-Yin Ng, Maryland Heights, MO (US);
Yun-Biao Xin, St. Peters, MO (US);
Henry Erk, St. Louis, MO (US);
Darrel Harris, Kirkwood, MO (US);
James Jose, Wentzville, MO (US);
Stephen Hensiek, Foley, MO (US);
Gene Hollander, Wentzville, MO (US);
Dennis Buese, O'Fallon, MO (US);
Giovanni Negri, Sizzano, IT;
MEMC Electronic Materials, Inc., St. Peters, MO (US);
Abstract
A process for forming a semiconductor wafer which is single side polished improves nanotopology and flatness of the polished wafer. The process reduces the effect of back side surface features, such as edge ring phenomena and back side laser marks, on nanotopology, thereby improving oxide layer uniformity for chemical/mechanical planarization (CMP) processing, and flatness on the polished front side of the wafer after polishing. The wafer is mounted on a polishing block by wax. The edge ring causes certain deformation and stress in the wafer upon mounting, which is held by the wax. After mounting, the wax is heated to allow the wafer to relax, removing the stress, without degrading the bond of the wafer to the polishing block. The wafer is polished and removed from the polishing blocks. The polished surface substantially retains its shape after being de-mounted from the block.