The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2002
Filed:
May. 27, 1999
Yai-Fen Lin, Taichung, TW;
Shiou-Hann Liaw, Hsiu-Chu, TW;
Di-Son Kuo, Hsinchu, TW;
Jian-Hsing Lee, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.