The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2002
Filed:
Apr. 03, 2000
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A new method of forming selective salicide is described, whereby low resistance salicide is formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without affecting device electrical performance. This invention describes a selective salicide process forming titanium salicide on exposed MOSFET CMOS devices using ion implantation for effective ion mixing between a two-step titanium deposition process. First, a thin layer of titanium is deposited on exposed polysilicon gate and exposed lightly doped source/drain (LLD) regions. Second, a low energy ion implantation of Si+ is performed with peak dose targeted to be just below the Ti/Si interface. Third, an initial rapid thermal anneal (RTA) is performed followed by a selective etch to remove unwanted, excess titanium. The final step is another rapid thermal anneal (RTA) to fully convert the silicide from C49 crystal structure to the preferred C54 structure, for low resistivity. Hence, low resistivity self-aligned silicide is formed on narrow polygates and lightly doped source/drains (LLD) without affecting device electrical performance.