The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2002
Filed:
Mar. 02, 1999
Dean J. Denning, Del Valle, TX (US);
Sam S. Garcia, Austin, TX (US);
Bradley P. Smith, Austin, TX (US);
Daniel J. Loop, Austin, TX (US);
Gregory Norman Hamilton, Pflugerville, TX (US);
Md. Rabiul Islam, Austin, TX (US);
Brian G. Anthony, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation ( ) on the inlaid structure in a chamber ( ). The RF preclean rounds corners ( and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces ( ). A tantalum barrier ( ) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer ( ), a copper seed layer ( ) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp ( ) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.