Process for making embedded dram circuits having capacitor under bit-line (cub)

Abstract

A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.