The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2002

Filed:

Feb. 02, 2000
Applicant:
Inventors:

Katsuomi Shiozawa, Tokyo, JP;

Takashi Kuroi, Tokyo, JP;

Yasuyoshi Itoh, Tokyo, JP;

Katsuyuki Horita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A semiconductor device includes a silicon substrate ( ), a pair of isolating insulation films ( ), a channel region ( ), a pair of source/drain regions ( ), a pair of silicon oxide films ( ) formed on an upper surface of the silicon substrate ( ) so as to overlie the source/drain regions ( ), and a gate structure ( ) formed in a first recess defined by the upper surface of the silicon substrate ( ) over the channel region ( ) and side surfaces of the pair of silicon oxide films ( ). The gate structure ( ) includes a gate oxide film ( ) formed on the upper surface of the silicon substrate ( ), a pair of silicon oxide films ( ) formed on lower part of the side surfaces of the pair of silicon oxide films ( ), and a metal film ( ) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films ( ), the silicon oxide films ( ) and the gate oxide film ( ). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.


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