The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2002
Filed:
Jun. 20, 2000
Jyh-Haur Wang, Hsin-Chu, TW;
Chih-Chiang Wang, Hsin-Chu, TW;
Hsien-Chin Lin, Hsin-Chu, TW;
Kuo-Hua Pan, Taichung, TW;
Carlos H. Diaz, Hsin-chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.