The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2002

Filed:

Oct. 29, 1999
Applicant:
Inventors:

Vincent J. McGahay, Poughkeepsie, NY (US);

John P. Hummel, Millbrook, NY (US);

Joyce Liu, Hopewell Junction, NY (US);

Rebecca Mih, Wappingers Falls, NY (US);

Kamalesh Srivastava, Wappingers Falls, NY (US);

Robert Cook, Minneapolis, MN (US);

Stephen E. Greco, LaGrangeville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
Abstract

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.


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