The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2001

Filed:

Apr. 01, 1999
Applicant:
Inventors:

Chia-Hsiang Chen, Hsin-Chu, TW;

Chih-Chien Hung, Hsin-Chu, TW;

Han-Ming Sheng, Hsin-Chu, TW;

Hsiang-Chung Liu, Jwu Beei, TW;

Chun-Mei Lee, Chu-Dung, TW;

De-Ming Liang, Hsin-Chu, TW;

Li-Kong Turn, Taichung, TW;

Ming-Huei Tseng, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K 9/32 ;
U.S. Cl.
CPC ...
G06K 9/32 ;
Abstract

A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.


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