The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2001

Filed:

Mar. 14, 1996
Applicant:
Inventors:

Syun-Ming Jang, Hsin-Chu, TW;

Chen-Hua Yu, Keelung, TW;

Lung Chen, Hsin-Chu, TW;

Lin-June Wu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/946 ; H01L 2/954 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/946 ; H01L 2/954 ;
Abstract

A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.


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