The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2001

Filed:

Aug. 25, 1999
Applicant:
Inventors:

Tony Lin, Kaohsiung Hsien, TW;

Alice Chao, Hsinchu, TW;

Jih-Wen Chou, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (V,) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the V,adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will. The subsequent process for the MOS transistor is then performed.


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