The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2001

Filed:

Oct. 19, 1999
Applicant:
Inventors:

Kevin Lucas, Austin, TX (US);

Olubunmi Adetutu, Austin, TX (US);

Christopher C. Hobbs, Austin, TX (US);

Yolanda Musgrove, Pflugerville, TX (US);

Yeong-Jyh Tom Lii, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 3/1062 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 3/1062 ;
Abstract

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (,) over a substrate (,). The MOS metallic gate electrode layer (,) is covered with an ARC layer (,). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (,and,) are then selectively masked photoresist (,) that is selectively exposed to deep ultraviolet (DUV) radiation (,). The ARC layer (,) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.


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