The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2001
Filed:
Nov. 09, 1999
Thomas P. Glenn, Gilbert, AZ (US);
Roy D. Hollaway, Paranaque, PH;
Amkor Technology, Inc., Chandler, AZ (US);
Abstract
A wafer-level method for mass production of surface-mounting, chip-size (“CS”) ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) semiconductor packages includes the wire-bond or flip-chip attachment of ceramic substrates to the active surface of corresponding chips while they are still integral to a semiconductor wafer, thereby reducing manufacturing costs of the packages relative to that of individually packaged chips. The substrates have a thermal coefficient of expansion (TCE) closely matching that of the underlying chip. This eliminates the need for a silicone “interposer” between the substrate and the chip otherwise necessary to prevent stress-related problems caused by the difference in the respective thermal expansion and contraction of the chip and substrate with changes in temperature, further reducing the cost of the packages, improving heat transfer from the chips, and resulting in a package that is relatively free of thermal-induced stresses.