Memory cell configuration and production process therefor

Abstract

A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate. Isolated word lines are provided which extend in the transverse direction along the main face for triggering the first and second selection transistors in the respective gate regions. Isolated bit lines are provided which extend in an oblique direction along the main face for connecting the first and second selection transistors in the respective source regions. And preferably ferroelectric capacitors are each connected to the drain regions of applicable selection transistors via capacitor contacts.