Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided hv transistors, and lv transistors with salicided junctions with few masks

Abstract

A method of forming source and drain regions for LV transistors that includes the steps of forming sacrificial spacers laterally to LV gate regions; forming LV source and drain regions in a self-aligned manner with the sacrificial spacers; removing the sacrificial spacers; forming HV gate regions of HV transistors; forming gate regions of selection transistors; forming control gate regions of memory transistors; simultaneously forming LDD regions self-aligned with the LV gate regions, HV source and drain regions self-aligned with the HV gate regions, source and drain regions self-aligned with the selection gate region and floating gate region; depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask; anisotropically etching the dielectric layer, to form permanent spacers laterally to the LV gate regions; removing the protection silicide mask; and forming silicide regions on the LV source and drain regions and on the LV gate regions.