Flash memory structure with stacking gate formed using damascene-like structure

Abstract

A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention. The disclosed method alleviates the problem of having poly residues resulting from defects caused by etching the conventionally deposited polysilicon layer. Furthermore, etching over active region can also cause damage to the underlying substrate, which is not the case here. In addition, the method enables the incorporation of the curved structure of the floating gate of this invention into the area that increases the coupling ratio of the flash memory cell.