The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
Mar. 18, 1999
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (<100Å). In order to etch the final portion of the polysilicon gate structure including an over etch to removed isolated polysilicon patches, an etchant containing HBr is used to provide a high polysilicon to gate oxide selectivity. This etch component causes a polymer veil to form over the surface of the photoresist which is difficult to remove except by aqueous etchants which also cause significant gate oxide loss. The method of the invention addresses the removal of the veil polymer, the photoresist, and a sidewall polymer by an all dry etching process. In a first all dry process, the residues and photoresist and sidewall polymers are removed in a commercial ICP plasma asher by a sequence of steps using O,/N,mixtures and a single O2/fluorocarbon step to remove the veil polymer. An alternate cleaning procedure removes the veil polymer with a O,/N,/H,gas mixtures at a low substrate temperature and the photoresist and sidewall polymers at a higher temperature. Maximum gate oxide loss by either method is less than 10 Å.