The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2001

Filed:

Mar. 31, 2000
Applicant:
Inventors:

Yoshiki Sota, Nara, JP;

Koji Miyata, Yao, JP;

Toshio Yamazaki, Tsukuba, JP;

Fumio Inoue, Tsukuba, JP;

Hidehiro Nakamura, Tsukuba, JP;

Yoshiaki Tsubomatsu, Tsuchiura, JP;

Yasuhiko Awano, Tsukuba, JP;

Shigeki Ichimura, Oyama, JP;

Masami Yusa, Shimodate, JP;

Yorio Iwasaki, Shimodate, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/3495 ; H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/3495 ; H01L 2/144 ;
Abstract

A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.


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