The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Mar. 25, 1999
Yun-Biao Xin, St. Peters, MO (US);
Ichiro Yoshimura, Tochigi, JP;
Henry F. Erk, St. Louis, MO (US);
Ralph V. Vogelgesang, Old Monroe, MO (US);
Stephen Wayne Hensiek, Foley, MO (US);
MEMC Electronics Materials, Inc., St. Peters, MO (US);
Abstract
A method for processing a semiconductor wafer sliced from a single-crystal ingot comprises subjecting the front and back surfaces of the wafer to a lapping operation to reduce the thickness of the wafer and to remove damage caused during slicing of the wafer. The wafer is then subjected to an etching operation to further reduce the thickness of the wafer and to further remove damage remaining after the lapping operation. The wafer is subsequently subjected to a double-side polishing operation to uniformly remove damage from the front and back surfaces caused by the lapping and etching operations, thereby improving the flatness of the wafer and leaving polished front and back surfaces. Finally, the back surface of the wafer is subjected to a back surface damaging operation in which damage is induced in the back surface of the wafer while the front surface is substantially protected against being damaged or roughened. A pressure jetting machine of the present invention includes a wafer holder that supports the wafer in the pressure jetting machine such that the back surface of the wafer is exposed to the jetted abrasive slurry while the front surface is supported by the holder in spaced relationship above a support surface of the machine to inhibit damaging engagement between the support surface and the front surface of the wafer.