The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2001
Filed:
Aug. 14, 1998
Hsiang Liu, Hsin-Chu, TW;
Chien-Ming Chung, Hsin-Chu, TW;
Liang Szuma, Taipei, TW;
Ding-Shan Wang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method is disclosed for sealing the edge of a wafer against slurry debris and contaminants that are encountered during grinding and backlapping of a semiconductor substrate. This is accomplished by depositing a photosensitive polyimide as a dielectric material on a wafer and mounting the wafer on a chuck. A light source is introduced above the wafer and close to the edge of the wafer. The chuck is then spun by means of a spindle, thus exposing an outer ring of the circumferential edge of the wafer to light source. Because polyimide behaves like a negative resist in the art of lithography, the exposed ring is fixed in place such that when the wafer is next developed, only the unexposed polyimide corresponding to the scribe line patterns is dissolved forming “scribe channels”, while leaving the ring in tact all along the circumference of the wafer. This wafer edge exposure (WEE) then forms an edge, which, in conjunction with a grinding tape, seals the perimeter of the wafer, thus preventing the polishing contaminants from entering the scribe channels.