The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2001
Filed:
May. 14, 1999
Gerrit Lange, München, DE;
Martin Franosch, München, DE;
Wolfgang Hönlein, Unterhaching, DE;
Volker Lehmann, München, DE;
Hans Reisinger, Grünwald, DE;
Herbert Schäfer, Höhenkirchen-Sieg.Brunn, DE;
Reinhard Stengl, Stadtbergen, DE;
Hermann Wendt, Grasbrunn, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p,/p,silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.