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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6162686 B1

PDFFull Text
Date of Patent:
Dec. 19, 2000

Filed:

Sep. 18, 1998

Method for forming a fuse in integrated circuit application

Applicant:
Inventors:

Kuo Ching Huang, Kaohsiung, TW;

Tse-Liang Ying, Hsin-Chu, TW;

Yu-Hua Lee, Hsinchu, TW;

Ming-Hsin Li, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;

Attorneys:

Saile; George O.

Ackerman; Stephen B.

Stoffel; William J.

Primary Examiner:

Trung Dang

Assistant Examiner:

Brook Kebede

Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
438281 ; 438132 ; 438333 ; 438601 ; 257503 ; 257506 ;
Abstract

A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.

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Huang, Kuo. (2000). Method for forming a fuse in integrated circuit application (U.S. Patent No. 6162686). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6162686

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