The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2000
Filed:
Dec. 29, 1999
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.