The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2000

Filed:

Jan. 20, 1999
Applicant:
Inventors:

Archibald John Allen, Shelburne, VT (US);

Jerome Brett Lasky, Essex Junction, VT (US);

Randy William Mann, Jericho, VT (US);

John Joseph Pekarik, Underhill, VT (US);

Jed Hickory Rankin, Burlington, VT (US);

Edward William Sengle, Hinesburg, VT (US);

Francis Roger White, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438230 ; 438233 ; 257900 ; 257903 ; 257344 ;
Abstract

A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.


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