The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2000

Filed:

Dec. 09, 1998
Applicant:
Inventors:

Chuan-Fu Wang, Taipei Hsien, TW;

Jason J Jenq, Pingtung, TW;

Benjamin Szu-Min Lin, Chiayi, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438238 ; 438253 ; 438396 ; 437 52 ;
Abstract

A method of manufacturing a DRAM capacitor comprises the steps of providing a substrate having a word line, a source/drain region, a bit line and a first insulator layer. A hard mask layer and a second insulator layer are formed on the first insulator layer in sequence. Next, an opening is formed to expose a portion of the first insulator layer by patterning the second insulator layer and the hard mask layer. Thereafter, a spacer is formed on the side wall of the opening and a node contact hole is formed to expose a portion of the source/drain region in the first insulator layer. The second insulator layer is stripped to expose the hard mask layer and a conductive layer is formed over the hard mask layer and fills the node contact hole. A bottom electrode is formed by patterning the conductive layer and a dielectric layer and another conductive layer are formed over the bottom electrode in sequence.


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