The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2000

Filed:

May. 15, 1998
Applicant:
Inventors:

David V Caletka, Apalachin, NY (US);

Jean Dery, Granby, CA;

Eric Duchesne, Granby, CA;

Michael A Gaynes, Vestal, NY (US);

Eric A Johnson, Greene, NY (US);

Luis J Matienzo, Endicott, NY (US);

James R Wilcox, Vestal, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257778 ; 257706 ; 257737 ;
Abstract

A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.


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