The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2000
Filed:
Sep. 03, 1999
Tsing-Fong Hwang, Tainan, TW;
United Semiconductor Corp., Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for fabricating a multilevel interconnect, where a first and a second conducting wires are formed respectively on a substrate, while a part of the substrate between the first and the second conducting wires is exposed. A first dielectric layer is then formed to cover the substrate as well as the first and the second conducting wires, wherein the first dielectric layer has an air gap formed between the first and the second conducting wires. An anti-etch layer is formed on the first dielectric layer above the air gap, while a second dielectric layer is then formed on the anti-etch layer and the first dielectric layer. A via opening which exposes the first conducting wire is then formed by etching, followed by forming a barrier layer which covers the profile of the via opening and the exposed surface of the first conducting layer. Consequently, a via plug is formed to fill the via opening.