The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2000
Filed:
Apr. 27, 1998
Charles Tyler Eytcheson, Kokomo, IN (US);
Monty Bradford Hayes, Kokomo, IN (US);
Lisa Ann Viduya, Carmel, IN (US);
Roger Allen Mock, Kokomo, IN (US);
Eric Von Kierstead, Anderson, IN (US);
Todd G Nakanishi, Noblesville, IN (US);
Robert John Campbell, Noblesville, IN (US);
Erich William Gerbsch, Brownsburg, IN (US);
Delco Electronics Corporation, Kokomo, IN (US);
Abstract
A parallel dual switch module that is characterized by improved mechanical and electrical packaging efficiency and low cost. The module includes a common terminal defined by a first stamped elongate metal plate insert molded into the module housing, and positive and negative terminals defined by second and third stamped elongate metal plates disposed side-by-side atop the common terminal. Connection areas formed on the positive and negative terminals extend in opposite lateral directions, and interdigitate with connection areas formed on the common terminal, thereby forming two linear parallel rows of connection areas. Adjacent each row of connection areas, and mounted on a baseplate of the module is a set of parallel connected transistors subassemblies. A molded elongate gate collection component is mounted on the baseplate between the sets of transistor subassemblies, and beneath the common terminal. The gate collection component confines a pair of insert molded gate terminal strips to which the gate terminals of the respective sets of transistor subassemblies are connected, and the terminal strips, in turn, are coupled to gate terminals of the module. The transistor subassemblies are mounted in close proximity to the central terminal structure, and the metal tabs of the subassemblies are shaped to prevent interference with the overlying terminal connection areas, and to provide stress relief.