Ferroelectric/high dielectric constant integrated circuit and method of

Abstract

A transistor on a silicon substrate is covered by an insulating layer. A conducting plug passes through the insulating layer to the transistor drain. The bottom electrode of a ferroelectric capacitor that directly overlies the plug and drain contacts the plug. The ferroelectric layer is self-patterned and completely overlies the memory cell. A self-patterned sacrificial layer completely overlies the ferroelectric layer. The bottom electrode of the capacitor is completely enclosed by the ferroelectric layer, the insulating layer, and the conducting plug. The sacrificial layer comprises either: a) a metal selected from a first metal group consisting of tantalum, hafnium, tungsten, niobium and zirconium; or b) a metallic compound comprising one or more metals selected from a second group of metals consisting of titanium, tantalum, hafnium, tungsten, niobium and zirconium compounded with one or more metals from a third group of metals consisting of strontium, calcium, barium, bismuth, cadmium, and lead, such as strontium tantalate, tantalum oxide, bismuth deficient strontium bismuth tantalate, strontium titanate, strontium zirconate, strontium niobate, tantalum nitride, and tantalum oxynitride.